DDRSREN=0, DDRPEN=0, PDBLOOP=0, RCRRSTEN=0, RCRRST=0, TRACECLKDIS=0, DDRS=0, DDRCFG=000, LCDSTART=0, ULPICLKOBE=0
Misc Control Register
| DDRSREN | DDR self refresh enable 0 (0): DDR is not set to self refresh mode. 1 (1): DDR is set in self refresh mode. Check DDRS to make sure DDR is in self refresh mode. |
| DDRS | DDR Self Refresh Status 0 (0): DDR is not set to self refresh mode. 1 (1): Sets DDR in self refresh mode. |
| DDRPEN | Pin enable for all DDR I/O 0 (0): All DDR I/O pins are disabled 1 (1): All DDR I/O pins are enabled |
| DDRDQSDIS | DDR_DQS analog circuit disable |
| RESERVED | no description available |
| DDRCFG | DDR configuration select 0 (000): LPDDR Half Strength 1 (001): LPDDR Full Strength 2 (010): DDR2 Half Strength 3 (011): DDR1 4 (100): Reserved 5 (101): Reserved 6 (110): DDR2 Full Strength 7 (111): Reserved |
| RCRRSTEN | DDR RCR Special Reset Enable 0 (0): No soft reset to DDR RCR 1 (1): Soft reset to DDR RCR |
| RCRRST | DDR RCR Reset Status 0 (0): DDR RCR is not in reset status 1 (1): DDR RCR is in reset status |
| RESERVED | no description available |
| LCDSTART | Start LCDC display 0 (0): Stops LCDC display 1 (1): Starts LCDC display |
| RESERVED | no description available |
| PDBLOOP | PDB Loop Mode 0 (0): Provides two seperated minor loop, loop for ADC0/1 and loop for ADC2/3D 1 (1): Provides a loop to involve ADC0, ADC1, ADC2 and ADC3. |
| ULPICLKOBE | 60 MHz ULPI clock (ULPI_CLK) output enable 0 (0): Internal generated 60MHz ULPI clock is not output to the ULPI_CLK pin. 1 (1): Interanl generated 60MHz ULPI clock provide clock for external ULPI phy. |
| TRACECLKDIS | Trace clock disable. 0 (0): Enables trace clock. 1 (1): Disable trace clock. |